1. Field of the Invention
The present invention relates generally to the fine tuning of a digitally controlled oscillator (DCO), and more particularly to reducing the complexity in implementing the fine tuning bank of an inductor/capacitor (LC)-tank DCO.
2. Description of the Related Art
All digital phase locked loops (ADPLLs) are used for various functions in a wide variety of electronic components, including for frequency synthesis for wireless transmission/reception in portable devices. The heart of the ADPLL is the digitally controlled oscillator (DCO). One way to implement a DCO is by using an LC oscillator which has two or more capacitance banks for digital tuning (an LC-tank DCO).
FIG. 1A is simple schematic of the tuning scheme of an LC-tank DCO, taken from FIG. 2.6.1 of L. Fanori et al., “3.3 GHz DCO with a Frequency Resolution of 150 Hz for All-Digital PLL,” IEEE ISSCC Tech. Dig., pp. 48-49, February 2010 (hereinafter, Fanori et al.), the contents of which are incorporated herein by reference. At the top is the impedance (LTank), with the Coarse Tuning capacitance bank below the LTank and the Fine Tuning capacitance bank at the bottom. The Coarse Tuning bank is used to compensate for process and temperature variations, while the Fine Tuning bank is used for DCO modulation inside the PLL.
The input to an LC-tank DCO is a frequency code word (fcw), made up of digital bits. Some of the bits in the fcw control the Coarse Tuning bank and some of the bits control the Fine Tuning Bank. In the example shown in FIG. 1B, taken from FIG. 2.6.2 of Fanori et al., the input fcw comprises two sets of bits C0, C1, . . . , C6, C7, and b0, b1, . . . , b11, b12. The eight bits C0, . . . , C7, are used to control the Coarse Tuning bank and the thirteen bits b0, . . . , b12 are used to control the Fine Tuning bank. Accordingly, each fcw can identify a specific capacitance.
How the thirteen bits b0, . . . , b12 control the Fine Tuning bank to generate different capacitances is indicated by the example of FIG. 1C, taken from FIG. 6 of L. Vercesi et al., “A Dither-less All Digital PLL for Cellular Transmitters,” in Proc. IEEE Custom Integrated Circuits Conf (CICC), pp. 1-8, September 2011 (hereinafter, Vercesi et al.), the contents of which are incorporated herein by reference. In FIG. 1C, a 16×16 capacitive element array for the Fine Tuning bank is shown, similar in appearance and control to a memory cell array, but used to generate specific capacitances corresponding to the input fcw. The thirteen-bit control word is broken in three, where bits b9, b10, b11, b12 are input to the row decoder (thereby picking one of 16 rows), bits b5, b6, b7, b8 are input to the column decoder (thereby picking one of 16 columns), and bits b0, b1, b2, b3 are input to a digital-to-analog converter (DAC) to provide 16 additional voltage levels at one varactor in the array (in black). Thus, a total of 12 DCO control bits are available, generating 4096 different levels of capacitance.
The Fine Tuning bank also uses thermometer coding. In general, thermometer coding represents (or “encodes”) a natural number n as n ones, which is either preceded by or followed by zeroes. The encoding can use n zeroes, or n−1 ones, or n−1 zeroes, etc., as would be known to one of skill in the art. In the Fine Tuning bank, thermometer coding means that every cell before the selected cell has one value and every cell after has another. In FIG. 1C, the top row is row 0 and bits b9, b10, b11, b12=0,1,0,1 are input to the row decoder, indicating row 5 (the 6th row down). In thermometer coding, rows 1-4 have to be turned on/off, or in this case, be grounded to Gnd as indicated by the grey color in FIG. 1C (this will be considered ON hereinafter while connected to a source voltage, in this case, Vdd, will be considered OFF). Bits b5, b6, b7, b8=0,1,1,1 are input to the column decoder, indicating column 7 (the eighth column). Under thermometer coding, every cell before that cell is ON and every cell after that cell is OFF. While the use of thermometer coding ensures monotonicity in such an array of capacitive unit cells, it also means that a large number of control lines is needed to control the unit cells.
Moreover, in this example, as shown in the upper right-hand corner of FIG. 1C, each cell requires a local decoder having an AND gate with the row and column line inputs (rj and ci) and an OR gate taking the output of the AND gate and the next row's input (rj+1). Thus, each row line has to drive double the load. In general, although the control lines are reduced in FIG. 1C, each control line is connected to more cells. Since a row control line is connected to all of the cells in that row, any activity to control a single cell acts as noise to the other cells. Furthermore, when dithering of the cells is required, and the cells need to turn on and off in a meandering pattern, the activity in the control lines is greatly increased.
In N. Da Dalt et al., “A 10b 10 GHz Digitally Controlled LC Oscillator in 65 nm CMOS,” IEEE ISSCC Tech. Dig., pp. 669-678, February 2006 (hereinafter, Da Dalt et al.), the contents of which are incorporated herein by reference, the columns of the capacitive array are divided into even and odd, thereby reducing the activity in each control line. However, two types of local decoder are needed, one for the even columns and one of the odd columns, and when metal-oxide-metal (MOM) capacitors are used, the different local decoders are placed under the MOM capacitors to save space, resulting in slightly different capacitances and more mismatches between capacitive cells.
Thus, there are several problems in designing a Fine Tuning capacitor bank for an LC-tank DCO. In general, there are usually too many control lines. See, e.g., C.-Y. Yao et al., “A 2.8-3.2-GHz fractional-N Digital PLL with ADC-assisted TDC and Inductively Coupled Fine-tuning DCO,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 698-710, 2013 (each cell requires 4 control lines, resulting in 128 control lines for a 10-bit capacitor array). Efforts to reduce the number of control lines result in the control lines having to drive larger loads, creating more noise in the array, and, when dithering, a great deal of activity toggling the fewer control lines resulting in more noise and power consumption. See, e.g., Vercesi et al. and Fanori et al. discussed above.
Accordingly, there is a need for systems, devices, and methods for reducing the control lines in the Fine Tuning bank of an LC-tank DCO, without increasing the complexity of the Fine Tuning bank circuitry, without increasing the load on the fewer control lines, and without greatly increasing activity when dithering.